Adam Teman

BIRAD - Research and Development Co. Ltd

Novel Transistor Gain Cell With Feedback

By Nati Fisher / December 18, 2020 / Comments Off on Novel Transistor Gain Cell With Feedback

Embedded memories, typically implemented with a 6T SRAM bitcell consume an ever growing share of the total silicon area and power. Gain cell embedded DRAM (GC-eDRAM) is an alternative to 6T SRAM, offering higher density, lower leakage, and 2-port operation. However, gain cells: Rely on dynamic storage Results in very low data retention times Increases…

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BIRAD - Research and Development Co. Ltd

Novel High-Density Memory Macro

By Nati Fisher / December 18, 2020 / Comments Off on Novel High-Density Memory Macro

The Problem Due to the growing demand for high-density embedded memories in modern microprocessors and other VLSI Systemon- Chip (SoC) designs, gain cell embedded DRAM (GCeDRAM) has emerged as an alternative to static random access memory (SRAM). GCeDRAM is known for its high-density, non-destructive read operation, low leakage power, and two-port operation. However, GCeDRAM requires…

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BIRAD - Research and Development Co. Ltd

Gain Cell Embedded Dram In Fully Depleted Silicon-On-Insulator Technology

By Nati Fisher / December 18, 2020 / Comments Off on Gain Cell Embedded Dram In Fully Depleted Silicon-On-Insulator Technology

The Problem As technology dimensions continue to scale down, high-density embedded memories are of great interest for many VLSI systems. However, 6T SRAM cells incur a large area penalty and suffer from high static power consumption in scaled CMOS nodes, often dominating the total area and power budget of a system. Gain-Cell embedded DRAM (GC-eDRAM)…

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BIRAD - Research and Development Co. Ltd

Cutting-Edge Complementary Dual Modular Redundancy Memory Cell

By Nati Fisher / December 18, 2020 / Comments Off on Cutting-Edge Complementary Dual Modular Redundancy Memory Cell

Embedded memories are often operated at scaled supply voltages in order to reduce their power consumption. However, reduction in the supply voltage also increases their susceptibility to soft errors. Soft errors occur when an energetic particle hits a reversed bias junction of an internal node in a memory cell, possibly flipping the data stored in…

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