As technology dimensions continue to scale down, high-density embedded memories are of great interest for many VLSI systems. However, 6T SRAM cells incur a large area penalty and suffer from high static power consumption in scaled CMOS nodes, often dominating the total area and power budget of a system. Gain-Cell embedded DRAM (GC-eDRAM) is an alternative to SRAM, featuring high density, non-destructive readout, low leakage, and two-port operation. However, GC‑eDRAM:
- Requires refresh cycles to maintain data, with the refresh operation becoming the main power consumer in deeply scaled technology nodes.
- Suffers from high access latency compared to SRAM due to degraded levels in the cell. Hence, large design guard bands and performance margins are needed to ensure reliable operation under process variability.
We propose a novel GC-eDRAM implementation in FD-SOI technology, which significantly improves the data retention time and access latency using body biasing.
The Commercial Benefit
Our cutting-edge, unique innovative structure:
- Enables the usage of body-bias to extend the cell’s DRT using reversed body bias
- Improves the read access latency using forward body bias.
- Provides per-bit error detection capabilities with low area overhead
- Offers 50% reduction in area over SRAM
- Allows 30% DRT improvement over conventional GC-eDRAM without body bias.
In 2017, global embedded systems market was valued at around USD 86 billion. This market is expected to reach USD 114 billion in 2024, growing at a CAGR of 4.0% between 2018 and 2024.
- Artificial intelligence
- Wireless communications
US patent application pending (17/257,893)
Team: Primary Inventor
Prof. Alexander Fish
Professor Alexander Fish is a Full Professor in the Faculty of Engineering at Bar-Ilan University and heads the Emerging NanoScaled Integrated Circuits and Systems (EnICS) Labs Impact Center, which he founded in 2015.
Professor Fish’s research interests include power reduction methodologies for high-speed digital and mixed-signal VLSI chips, energy efficient SRAM and eDRAM memory arrays, CMOS image sensors and biomedical circuits, systems, and applications, and hardware security. He has authored and co-authored over 170 scientific papers in journals and conferences. He has also submitted more than 30 patent applications. Professor Fish has published three book chapters and one book as an editor.
Professor Fish founded and served as an Editor-in-Chief for the MDPI Journal of Low Power Electronics and Applications (JLPEA) from 2012 to 2018. He is an Associate Editor for the IEEE Sensors Journal, the IEEE Access Journal, Microelectronics Journal (Elsevier) and Integration, and the VLSI Journal (Elsevier).
Professor Fish is a member of the Sensory, VLSI Systems and Applications and Bio-Medical Systems Technical Committees of IEEE Circuits and Systems Society.
Dr. Adam Teman
Dr. Adam Teman is a Tenure Track Senior Lecturer in the Faculty of Engineering at Bar-Ilan University and a Co-Director of the Emerging NanoScaled Integrated Circuits and Systems (EnICS) Labs Impact Center. Dr. Teman's research interests include embedded memories, energy-efficient circuit design, hardware for artificial intelligence, hardware acceleration, and methodologies for physical implementation. He has authored over 70 scientific papers and many patent applications and has participated in over 15 IC tapeouts. Dr. Teman is a primary investigator in grant programs from the Israel Innovation Authority, Israeli Science Foundation, and others. Dr. Teman has been awarded several prestigious awards, including a Swiss Government Excellence Scholarship, a Wolf Foundation Scholarship, and the Intel Prize. Dr. Teman is an associate editor at the Microelectronics Journal and a member of the technical and review boards of several conferences and journals. He is the co-author of the recently published book "Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip", available from Springer.
Development and optimization of advanced features in 28nm silicon.
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