Embedded memories are often operated at scaled supply voltages in order to reduce their power consumption. However, reduction in the supply voltage also increases their susceptibility to soft errors. Soft errors occur when an energetic particle hits a reversed bias junction of an internal node in a memory cell, possibly flipping the data stored in it. Embedded memory errors are typically handled at an architectural level with error-correction-codes or triple-modular redundancy, incurring high area overhead, delay, and complexity.
Our proposed novel, complementary dual modular redundancy (CDMR) memory is based on a four transistor dynamic memory core that internally stores complementary data values to provide an inherent per-bit error detection capability.
The Commercial Benefit
By adding simple, low-overhead parity, our memory:
- Has an added error-correction capability
- Displays as much as 3.5x smaller silicon footprint than other radiation-hardened bitcells (when implemented in a 65nm CMOS technology)
- Saves between 48%-87% standby power than other considered solutions across the entire operating region
The non-volatile memory market is expected to be worth USD 82.03 Billion by 2022, at a CAGR of 9.50% between 2017 and 2022. The growth of this memory market is driven by customers' need for high-speed, low-power-consuming, and highly scalable memory devices.
- Artificial intelligence
- Wireless communications
US granted patent number 10,991,421
Team: Primary Inventor
Prof. Alexander Fish
Professor Alexander Fish is a Full Professor in the Faculty of Engineering at Bar-Ilan University and heads the Emerging NanoScaled Integrated Circuits and Systems (EnICS) Labs Impact Center, which he founded in 2015.
Professor Fish’s research interests include power reduction methodologies for high speed digital and mixed-signal VLSI chips, energy efficient SRAM and eDRAM memory arrays, CMOS image sensors and biomedical circuits, systems and applications, and hardware security. He has authored and co-authored over 170 scientific papers in journals and conferences. He has also submitted more than 30 patent applications. Professor Fish has published three book chapters and one book as an editor.
Professor Fish founded and served as an Editor-in-Chief for the MDPI Journal of Low Power Electronics and Applications (JLPEA) from 2012 to 2018. He is an Associate Editor for the IEEE Sensors Journal, the IEEE Access Journal, Microelectronics Journal (Elsevier) and Integration, and the VLSI Journal (Elsevier).
Professor Fish is a member of the Sensory, VLSI Systems and Applications, and Bio-Medical Systems Technical Committees of IEEE Circuits and Systems Society.
Dr. Adam Teman
Dr. Adam Teman is a Tenure Track Senior Lecturer in the Faculty of Engineering at Bar-Ilan University and a Co-Director of the Emerging NanoScaled Integrated Circuits and Systems (EnICS) Labs Impact Center. Dr. Teman's research interests include embedded memories, energy efficient circuit design, hardware for artificial intelligence, hardware acceleration, and methodologies for physical implementation. He has authored over 70 scientific papers and many patent applications and has participated in over 15 IC tape outs. Dr. Teman is a primary investigator in grant programs from the Israel Innovation Authority, Israeli Science Foundation, and others. Dr. Teman has been awarded several prestigious awards, including a Swiss Government Excellence Scholarship, a Wolf Foundation Scholarship, and the Intel Prize. Dr. Teman is an associate editor at the Microelectronics Journal and a member of the technical and review boards of several conferences and journals. He is the co-author of the recently published book "Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip", available from Springer.
Migration and adjustment to under 10nm technologies
Investors are invited to license our patent through a licensing agreement with sponsored research.