The Problem

Due to the growing demand for high-density embedded memories in modern microprocessors and other VLSI Systemon- Chip (SoC) designs, gain cell embedded DRAM (GCeDRAM) has emerged as an alternative to static random access memory (SRAM). GCeDRAM is known for its high-density, non-destructive read operation, low leakage power, and two-port operation. However, GCeDRAM requires periodic refresh cycles to reliable retain data, both reducing the memory availability and consuming dynamic refresh power. While GC-eDRAM Implementations in mature technology nodes, such as 90 nm and 65 nm, provides long data retention time (DRTs), sub nm technologies suffer from much shorter DRTs due to the reduced parasitic storage capacitances and increased leakage currents.

The Commercial Benefit

Our innovative memory macro:

• Is fully logic compatible
• Provides dual-ported functionality
• Can be operated at above 500Mhz
• Provides over 30% lower area and power compared to an SRAM memory in the same
  technology
• Contains high-speed differential sense amplififier and low-threshold readout transistors for improved access time
• Contains level converting write drivers for improved write in terms of both speed and level passing

The proposed technology was fabricated in a 28nm CMOS bulk process, demonstrating up-to 800 MHz operating frequency, over 10us of data retention time, and a 30% area reduction over conventional SRAM memories.

Team: Primary Inventor

Prof. Alexander Fish
Professor Alexander Fish is a Full Professor in the Faculty of Engineering at Bar-Ilan University and heads the Emerging NanoScaled Integrated Circuits and Systems (EnICS) Labs Impact Center, which he founded in 2015.
Professor Fish’s research interests include power reduction methodologies for high speed digital and mixed signal VLSI chips, energy efficient SRAM and eDRAM memory arrays, CMOS image sensors and biomedical circuits, systems and applications and hardware security. He has authored and co-authored over 170 scientific papers in journals and conferences. He has also submitted more than 30 patent applications. Professor Fish has published three book chapters and one book as an editor.
Professor Fish founded and served as an Editor-in-Chief for the MDPI Journal of Low Power Electronics and Applications (JLPEA) from 2012 to 2018. He is an Associate Editor for the IEEE Sensors Journal, the IEEE Access Journal, Microelectronics Journal (Elsevier) and Integration, and the VLSI Journal (Elsevier).
Professor Fish is a member of the Sensory, VLSI Systems and Applications and Bio-Medical Systems Technical Committees of IEEE Circuits and Systems Society.

Dr. Adam Teman
Dr. Adam Teman is a Tenure Track Senior Lecturer in the Faculty of Engineering at Bar-Ilan University and a Co-Director of the Emerging NanoScaled Integrated Circuits and Systems (EnICS) Labs Impact Center. Dr. Teman's research interests include embedded memories, energy-efficient circuit design, hardware for artificial intelligence, hardware acceleration, and methodologies for physical implementation. He has authored over 70 scientific papers and many patent applications and has participated in over 15 IC tapeouts. Dr. Teman is a primary investigator in grant programs from the Israel Innovation Authority, Israeli Science Foundation, and others. Dr. Teman has been awarded several prestigious awards, including a Swiss Government Excellence Scholarship, a Wolf Foundation Scholarship, and the Intel Prize. Dr. Teman is an associate editor at the Microelectronics Journal and a member of the technical and review boards of several conferences and journals. He is the co-author of the recently published book "Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip", available from Springer.