HiPer SoC Lab announces its first SoC platform designed in close collaboration with Cadence, imec and TSMC

BIRAD - Research and Development Co. Ltd

 Ramat Gan, Israel,

The HiPer Consortium SoC Lab of Bar Ilan University, together with its partners, Cadence Design Systems, imec and TSMC, announced today the successful bring-up and validation of its 28nm system-on-chip (SoC) platform, which provides a foundation for collaborative innovation in advanced process nodes.

The SoC Lab, funded by the Magnet Program of the Israel Innovation Authority in the framework of the HiPer Consortium, was established to address multiple challenges of SoC design. This is Israel’s first scaled SoC design, implementation and measurement laboratory that ties academic research to industrial requirements.

The 28nm SoC is the HiPer SoC Lab’s first project and the fruition of extensive design effort and collaboration, covering all the design aspects from architecture definition to silicon validation. It integrates complex digital and analog intellectual property (IP) such as control processor, network-on-chip (NOC) interconnect fabric and advanced analog front-end (AFE). This platform is used to characterize and test new developments in a system level environment, as well as to develop and practice advanced design flows and methodologies. This project sets the infrastructure for future collaborative industry-academia SoC-related research and development in scaled process nodes.

The 28nm SoC project is the result of a unique partnership and close collaboration between the HiPer SoC Lab and major players in the semiconductor industry ecosystem.

“We appreciate the contributions from all of our industry partners to the success of the SoC Lab”, said Professor Alexander Fish at Bar-Ilan University. “We are looking forward to continue and further develop this unique academia-industry cooperation in our next projects”.

The design and verification know-how that was gathered during this project, along with the IP validated upon the SoC platform, will be used by the Israeli microelectronics industry for commercial products.

Cadence, via its Cadence Academic Network, supported the tapeout by providing licenses of its Cadence® digital and signoff solutions. Additionally, Cadence Design IP, such as Ethernet Controller and PHY, were integrated in the design. For the hardware/software co-verification, the Cadence Palladium® hardware emulator platform was deployed. During the tapeout phase, the company offered their extensive engineering expertise. The combination of the company’s software, services, Design IP and Palladium platform enabled the first-time-right silicon success.

“The HiPer Consortium project is a fantastic example of how academia and industry can work together and exchange expertise to support design innovations,” said Sanjay Lall, Vice President of Worldwide Field Operations for Cadence EMEA. “With this success, the Israeli microelectronics industry has received an important platform to address advanced SoC design. We are excited to be part of the next projects with our collaboration partners.”

Cadence, the world-leading research and innovation hub in nanoelectronics and digital technologies, provided the foundry tapeout support and low-cost prototyping services through its imec.IC-link program.

“imec.IC-link is proud to be part of this HiPer SoC Lab initiative. In a spirit of collaborative innovation, HiPer is bridging the gap between academia and industry. The accumulated experience will lower the barrier for startups and SME’s, to gain access to advanced ASIC technology”, said Steve Beckers, VP at imec and GM of imec.IC-link.

TSMC, the world’s largest dedicated semiconductor foundry, provided access to its 28nm HPM process technology design kit, including standard cell libraries, memory compilers, I/O libraries and provided foundry services.

“I congratulate the HiPER consortium on the successful launch of its design Platform, which offers new designers a fast route to silicon success”, said Maria Marced, President TSMC Europe. “This design platform will showcase the innovation of the Israeli design community. As the world’s leading semiconductor foundry, TSMC is happy to offer our technology leadership as well as manufacturing excellence, and we look forward to further close collaboration.”



About HiPer Consortium
The HiPer consortium is involving industrial companies and academic research to push the VLSI/SoC performance boundaries and achieve a much better, cheaper and faster R&D process and chips. The HiPer consortium has set the following long term strategic goals:

  • Cut by 50% the time that takes to design and integrate a complex SoC chip.
  • Get a working chip in the first Fab round.
  • Improve the system performance by 30% without compromising on area and power.

To achieve the above goals, the HiPer consortium is conducting cutting edge R&D work in the following technological areas:

  • Establish and implement SoC laboratory in Bar Ilan University that will develop the required infrastructure, tools and knowledge for the rapid integration of SoC in 28nm or smaller geometries.
  • Develop new methods and algorithms for the efficient and rapid data transfer in parallel processing and multicore heterogeneous devices.
  • New and efficient models for the implementation of rapid and cost effective memory models for SoC implementations.
  • Research new models and algorithms to accelerate the performance of multi core, DSP based systems.
  • Research and develop novel methods to conduct process node comparison to match the best fabrication process for a given set of requirements.
  • Develop methods and tools for an early evaluation of system performance

More information about the Hiper consortium is available at www.hiper.org.il

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine’s 100 Best Companies to Work For. Learn more at www.cadence.com

About imec
Imec is the world-leading research and innovation hub in nanoelectronics and digital technologies. The combination of our widely acclaimed leadership in microchip technology and profound software and ICT expertise is what makes us unique. By leveraging our world-class infrastructure and local and global ecosystem of partners across a multitude of industries, we create groundbreaking innovation in application domains such as healthcare, smart cities and mobility, logistics and manufacturing, and energy.

As a trusted partner for companies, start-ups and universities we bring together close to 3,500 brilliant minds from over 75 nationalities. Imec is headquartered in Leuven, Belgium and also has distributed R&D groups at a number of Flemish universities, in the Netherlands, Taiwan, USA, China, and offices in India and Japan. In 2016, imec’s revenue (P&L) totaled 496 million euro. Further information on imec can be found at www.imec.be 

Imec is a registered trademark for the activities of IMEC International (a legal entity set up under Belgian law as a “stichting van openbaar nut”), imec Belgium (IMEC vzw supported by the Flemish Government), imec the Netherlands (Stichting IMEC Nederland, part of Holst Centre which is supported by the Dutch Government), imec Taiwan (IMEC Taiwan Co.) and imec China (IMEC Microelectronics (Shanghai) Co. Ltd.) and imec India (Imec India Private Limited), imec Florida (IMEC USA nanoelectronics design center).


About TSMC

TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry segment’s largest portfolio of process-proven libraries, IPs, design tools and reference flows. The Company’s owned capacity in 2017 is expected to reach above 11 million (12-inch equivalent) wafers, including capacity from three advanced 12-inch GIGAFAB® facilities, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC China. TSMC is the first foundry to provide both 20nm and 16nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please visit http://www.tsmc.com.



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Dr. Tsvika Ben-Porat

Dr. Ben Porat is an experienced veteran of Israel’s high-tech. He was the CTO of Ness Technologies (formerly traded on NASDAQ: NSTC), Founder of dbMotion (Sold to AllScript for $235MM). He was the CEO of Maayan Ventures, the largest technology incubator in Israel (taken public on the TASE) and the CEO of Jerusalem Technology Investment Ltd. (JTI) (Traded on the TASE). Dr. Ben Porat holds a Ph.D. in physics from Ben-Gurion University as well as a Ph.D. in Business Administration from Ben-Gurion University. He served in the Israeli Air Force